Trends in modern integrated circuitry are generally towards smaller size (miniaturization) and greater function (increased circuit density). Generally, greater functionality indicates a required increase in input/output (I/O) connections (e.g., bond pads) on the die. As integrated circuit devices become smaller and their function increases, the need arises for improved methods of forming large numbers of connections between an integrated circuit die and its package. Traditional techniques for connecting (e.g., a lead frame, or the like) to a semiconductor die include wire bonding and tape-automated bonding. Generally, both of these techniques are relatively large in scale as compared with the bond pads on the die, and are not shrinking significantly. Hence, generally, techniques for connecting to a semiconductor die are not keeping apace of integrated circuit miniaturization.
The number of external interface (e.g., I/O) signals on integrated circuit dies has increased steadily to a point where it is not uncommon to find 200 or more "pins" (i.e., I/O connections) on modern integrated circuits, particularly on very large-scale integrated circuits such as high-end microprocessors. Miniaturization demands that these increasing numbers of connections be formed in ever-smaller areas.
Another trend in modern integrated circuits has been toward providing larger numbers of external interface (I/O) signals for a given amount of circuitry. While decreasing semiconductor device geometries (increasing circuit densities) have accommodated demands for greater amounts of circuitry in a given semiconductor die area, I/O signals are generally limited in number by the space along the periphery (edges) of the die. This is because "bond pads" to which external I/O signal connections are made, are typically placed along the edges of the die. While some attempts have been made to utilize portions of the interior area of the die for bond pads, problems associated with long bond wire runs and bond wires crossing over other bond wires tend to render these approaches cumbersome and impractical.
Co-pending commonly owned U.S. patent application Ser. No. 07/916,328 filed Jul. 17, 1992 by Rostoker, now U.S. Pat. No. 5,340,772 (hereinafter ROS1) describes a technique whereby greater numbers of bond pads per unit of semiconductor die area can be achieved by making use of "certain non-square" die shapes such as triangle shapes, trapezoidal shapes, greatly elongated rectangular shapes, parallelogram shapes, etc.. Compared to low-aspect ratio rectangular shaped or square semiconductor dies, these certain non-square die shapes exhibit an inherently greater ratio of edge length to surface area, permitting more bond pads to be placed in the peripheral area of the die (just inside the edges thereof) per unit of die area.
Conventional integrated circuit packages commonly have a square or low-aspect ratio rectangular "die-receiving area". The die-receiving area, into which a semiconductor die is mounted, is generally defined as the area described (contained within) the inner ends of conductive lead fingers (or conductive traces) of the package (or leadframe).
The conductive traces (e.g., lead fingers) of a semiconductor package extend outward from the die-receiving area, ultimately ending at and providing electrical connection to the external leads, pins or the like of the semiconductor package. In some cases, the conductive traces of the package radiate (fan) outward from the die-receiving area, being most closely packed where they are closest to the die. The physical constraints on trace size and pitch (spacing) clearly limit how many traces can fit adjacent to the die-receiving area. It is known, that by terminating some or all of the traces at a distance from the die-receiving area, the number of traces can be increased. However, when connecting a bond wire between the die and the trace, the lengths involved can quickly become unacceptable.
Copending, commonly-owned U.S. patent application Ser. No. 07/933,430 filed Aug. 21, 1992 by Rostoker, now U.S. Pat. No. 5,329,157 (hereinafter ROS2) describes semiconductor packages with "certain non-square" die-receiving areas to accommodate certain non-square die shapes, such as those described in ROS1. ROS2 provides for highly optimal mounting and connection arrangements for certain non-square dies which are particularly well suited to mounting non-square dies by matching the shape of the die-receiving area, as defined by the inner ends of the conductive traces, to the (certain non-square) shape of the die.
Irrespective of the type of package (e.g., conventional or ROS2-type packages) and style of die mounting, the semiconductor die must be connected to inner ends of the conductive lead fingers in the package. One well-known way to effect this connection is by using bond wires attached at one end to bond pads on the die, and attached at their other end to the inner ends of the lead fingers. Bond wires are on the order of one thousandth of an inch, or less, in diameter. Bond pads are on the order of a few thousandths of an inch, spaced from one another on the order of one thousandth of an inch. Evidently, when many bond wires are connected to a die, this is a very crowded situation, and there is the possibility of these bond wires shorting against one another, breaking, and other related problems. This problem is exacerbated in plastic molded packaging, wherein a die is mounted to a lead frame, wire bonded thereto, inserted into a mold, and covered with plastic. The influx of plastic into the mold can cause movement of the closely-spaced bond wires, resulting in a defective packaged component. Coming this late in the process (during packaging), defects due to bond failure are generally irreversible and expensive. Semiconductor die shape notwithstanding, the trend in microelectronics towards smaller, denser semiconductor dies with more input/output (I/O) connections causes increased difficulty in packaging such dies, especially in plastic packages, due to lead frame and bonding limitations.
There is a tremendous hesitancy in the semiconductor industry to use "non-standard" packages or packaging equipment, largely due to issues of tooling, capital equipment cost and training. In other words, the familiar is favored over the unfamiliar. This means that, at least in the short-term, the industry could find it advantageous to package the "certain non-square" dies of ROS1 in conventional packages, rather than in the non-conventional packages of ROS2. Unfortunately, the shape mismatch between the "certain non-square" dies of ROS1 and the die-receiving areas of conventional packages inevitably creates situations where some "bond wires" between bond pads on the (certain non-square) semiconductor die and the die-receiving area of the package are "unacceptably" long. Such bond wires become "unacceptably" long when there is a significant danger of shorting between adjacent bond wires.
Having overly long bond wires can cause other problems besides shorting together. For example, bond wires, as mentioned hereinabove, are extremely fine wires of about 0.001 inches in diameter. At extended lengths (e.g., twice "normal"), such bond wires can exhibit sufficient resistance to cause voltage drops when carrying current. Further, the increased resistance exhibited by long bond wires can interact with parasitic capacitances in the die and/or the package to cause RC (resistive-capacitive) delays, thereby slowing the operation of the packaged die. Inconsistent wire lengths can also contribute to signal "skewing" due to differential signal delay times experienced by one lead of the package vis-a-vis other leads.